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Professor: Christian Piguet
Tipo di corso: Lecture
Valore in crediti ECTS: 6
Academic year 2012/2013 - Fall semester
Objective
This course describes microelectronic technologies used to implement integrated
circuits. The course contains 4 chapters. The two first chapters describe
the design of layout and CMOS circuits in a bottom–up approach. It starts
with the first chapter in which layout design is presented while using old but
simple technologies to be clearer. The second chapter describes the design of
simple CMOS circuits using simple methods that directly give transistor schematics.
Basic cells that can be found today into standard cell libraries will be
designed as examples. The two last chapters are focused on deep submicron
technologies as well as on low-power design. The SIA Roadmap will be presented.
It describes the possible evolution of microelectronic technologies for
the next 15 years and the problems that will occur. The use of such technologies
for SoC (Systems-on-Chips) is mandatory, as these SoC will contain a very
large number of transistors. One obvious problem is the power consumption,
and the fourth chapter will describe the power consumption issues and the
possible solutions at circuit and layout levels.
Contents
Layout Design
1. Introduction to IC Technologies
2. Layout, Masks, Fabrication, Layout Rules
3. MOS Transistor, Logical and Delay Models, Logic Gates
Design of CMOS Cells
- Design of static CMOS cells
- Design of dynamic CMOS circuits
- Design of SRAM and ROM memories and FPGA
- Design of Flip-Flops and Finite State Machines
- Design of arithmetic circuits
Microelectronic Technology Evolution
- ITRS Technology Status and Evolution towards Deep Submicron
- Power Consumption
- Leakage reduction at circuit and architecture levels
- SOI technology and new devices
- Technology variations
- Alternating technologies
- Interconnect delays
Low-Power Design at Circuit and Layout Levels:
- power and Energy, Power Reduction from High to Low Level
- Architecture Level: activity reduction, low activity code, gated clocks, asynchronous
- Architecture Level: Vdd reduction, pipelining, parallelisation, adiabatic
- Architecture Level: capacitance reduction, simplicity
- Low level: latch design, activity reduction, gated clocks, glitches
- Low level: Vdd and VT reduction
- Low level: capacitance reduction, low-power library
Practice: student tools called Microwind and Dsch. See www.microwind.org
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