Sezione 1. Pubblicazioni all'USI di Francesco Regazzoni
Lista delle pubblicazioni
Pubblicazioni principali
Giaconia M., Macchetti M., Regazzoni F., Schramm K. (2007). Area and Power Efficient Synthesis of DPA-Resistant Cryptographic SBoxes. in proceedings of International Conference on VLSI Design & Embedded Systems, January 6-10, 2007, Bangalore - India .
Nacul A., Regazzoni F., Lajolo M. (2007). Hardware Scheduling Support in SMP Architectures. Accepted for Pubblication at Design, Automation and Test in Europe (DATE) 2007, 16-20 April, Nice, France .
Chandra S., Regazzoni F., Lajolo M. (2006). Hardware/Software Partitioning of Operating Systems: a Behavioral Synthesis Approach. In Proceedings of GLSVLSI 2006
pp. 324-329, Philadelphia, PA (U.S.A.), April 30 - May 2, 2006..
Bertoni G., Breveglieri L., Farina R., Regazzoni F. (2006). Speeding Up AES By Extending a 32 bit Processor Instruction Set. in proceedings of ASAP 2006, Steamboat Springs, Colorado - USA.
Regazzoni F., Lajolo M. (2005). Hardware/Software Partitioning and Interface Synthesis in Networks On Chip. n proceedings of IP Based SoC Design 2005, Grenoble, France, December 7-8, 2005.
Conferenze con proceedings
Fiorin L., Ferrante A., Padarnitsas K., Regazzoni F. (2012). Security Enhanced Linux on Embedded Systems: a Hardware-accelerated Implementation. ASP-DAC.
Giaconia M., Macchetti M., Regazzoni F., Schramm K. (2007). Area and Power Efficient Synthesis of DPA-Resistant Cryptographic SBoxes. in proceedings of International Conference on VLSI Design & Embedded Systems, January 6-10, 2007, Bangalore - India .
Nacul A., Regazzoni F., Lajolo M. (2007). Hardware Scheduling Support in SMP Architectures. Accepted for Pubblication at Design, Automation and Test in Europe (DATE) 2007, 16-20 April, Nice, France .
Chandra S., Regazzoni F., Lajolo M. (2006). Hardware/Software Partitioning of Operating Systems: a Behavioral Synthesis Approach. In Proceedings of GLSVLSI 2006
pp. 324-329, Philadelphia, PA (U.S.A.), April 30 - May 2, 2006..
Bertoni G., Breveglieri L., Farina R., Regazzoni F. (2006). Speeding Up AES By Extending a 32 bit Processor Instruction Set. in proceedings of ASAP 2006, Steamboat Springs, Colorado - USA.
Regazzoni F., Nacul A., Lajolo M. (2005). Automatic Synthesis of the Hardware/Software Interface in Multiprocessor Architectures. n proceedings of FDL'05 - Forum on Specification and Design Languages Lausanne, Switzerland, September 27-30, 2005.
Regazzoni F., Lajolo M. (2005). Hardware/Software Partitioning and Interface Synthesis in Networks On Chip. n proceedings of IP Based SoC Design 2005, Grenoble, France, December 7-8, 2005.
Regazzoni F., Lajolo M. (2004). Interface Synthesis in Multiprocessing Systems-on-Chips. proceedings at IP Based SoC Design 2004, Grenoble, December 2004..