Network-on-Chips

Professor: Luca Benini

Course type: Lecture
Value in ECTS: 3


Academic year 2012/2013 - Spring semester


Overview of the course
Designing System-On-Chips (SOCs) based upon reusable IP cores is essential for meeting stringent timeto-market requirements. Once suitable IP cores are identified, the focus shifts to the integration challenge: how to build a working system from a collection of generic and domain-specific cores that were not designed to work together. This requirement separates SOC designs from traditional block-based ASICs. The major challenge designers of this system must overcome will be to provide for functionally correct, reliable operation of the interacting components. One of the main challenges that silicon technologies will have to face is that synchronisation of future chips with a single clock source and negligible skew will be extremely difficult, if not impossible. The most likely synchronisation paradigm for future system chips – globally asynchronous and locally synchronous – involves using many different clocks. In the absence of a single timing reference, SOCs become distributed systems on a silicon substrate. The global communication pattern will be fully distributed, with little or no global coordination. After introducing some necessary fundamental concepts, this course presents and discusses major aspects of Networks on Chip design: integration (mapping) of functional and architectural specification, SOC communication architectures, communication trade-offs.


Contents

  1. Introduction
    1.1 Overview of the SOC Design Process
    1.2 Integration Platforms and SOC Design
    1.3 Function-Architecture Codesign
  2. SOC communication architectures
    2.1 Overview of SOC Communications
    • Buses (peripheral buses, packet networks, pipelined buses, …)
    • VSI Alliance´s Virtual Component Interface
    • Silicon Backplane Network (Sonics Networks) i. Open Core Protocol (Arbitration, TDMA, …)
    • IBM´s CoreConnect
    • Xilinx Virtex-II Pro
    2.2 Memory Sharing
    2.3 DMA And Bridge Architectures
    2.4 Design Space Exploration
  3. CAD methodologies
    3.1 Functional and Architectural Specifications
    3.2 Mapping High-level Design Transactions to Bus Architectures
    3.3 State of the Art Tools (Cadence VCC, Coware, Mathworks, …)
    3.4 Developing an Integration Platform
    • Emphasis on the CAD tool used in the practical training

Teaching mode
Theoretical lectures are supported by practical training on the usage of a CAD tool for system-level design that will be provided to the students.