Embedded Processor Design and programming
Academic year 2012/2013 - Spring semester
Part 1: Peter Marwedel and Heiko Falk
This course focuses on compiler techniques needed to adapt the execution of algorithms to embedded processor architectures. The overall goal is to provide insight into the mutual dependencies of architectural processor features and efficient algorithm implementation. First of all, the course includes techniques for dealing with the memory wall problem (the problem resulting from memories as performance bottlenecks). Next, we consider worst case execution times (WCETs). Such WCETs are important for applications with real-time constraints. Techniques for estimating and for optimizing WCETs are presented. The presented techniques allow for an early checking of worst case execution times.
In-line with the course synopsis, the first part of the course consists of the following content:
- We start out with techniques for adapting algorithms to the memory architectures:
- Introduction: Relevant design objectives (e.g. energy consumption, delay), Memory hierarchies
- Scratch pad memories (SPMs): characteristics, optimisation techniques with and without automatic overlays; Tools: SPM tools from Dortmund, integer linear programming tools (e.g. lp_solve)
- Adapting algorithms to cache architectures
- Other instances of taking the memory hierarchy into account
- Then, we present techniques for optimising WCETs for processor architectures
- Introduction: Definitions, problems Techniques for computing WCETs for given programs and architectures Tools: integer linear programming tools (e.g. lp_solve)
- Techniques for adapting applications to architectures, aiming at minimizing WCETs
There will be an associated lab. In this lab an available compiler infrastructure will be used to demonstrate the design of optimisation techniques presented in the classroom. Projects will include experiments with Olive and Lance and simple optimisation algorithms. During some of the days, labs and lectures may be swapped. Evaluation of the students will be based on their performance during the lab and in a written exam.
Part 2: Rainer Leupers
This course discusses C compiler generation for embedded processors as well as advanced code optimisation techniques for DSPs and VLIWs. It is complemented with practical lab sessions using industry standard design tools (Synopsys Compiler Designer, ACE CoSy).
- Compiler generation for embedded processors
- Code selection techniques
- DSP address code optimisation
- Code optimisation for SIMD instructions
- Code optimisations for conditional instructions
- Source level code optimisation for DSP